flocking演算法

① unity3d 怪物隨機走動為什麼怪物只在原地走動

ai是個復雜的實現。 1。狀態轉換。例如被攻擊後轉向敵人，釋放魔法後進去休息狀態，敵人過於強大ai會逃跑，這些問題首先直觀的使用if else語句，可以這樣的ai通常非常難以寫出來，而且ai的修改會很麻煩，這時候業內慣用「有限狀態機」解決此問題。 2。路徑規劃。怎樣從A點到B點要繞過中間的障礙物，這需要演算法解決，非常成熟的解決方案就是 A＊尋路（A星尋路演算法），這中演算法適合解決固定障礙的路徑規劃，如繞過山，河，溝不可移動的障礙。另外點下更復雜的戰術式尋路，如避開敵人火力區的路線，避開地面雷達的飛行路線等。 3。避開障礙物體。其實這也屬於「路徑規劃」類的問題，只不過此問題解決的是動態的障礙，和上面的第2點有非常大的區別。如20或者200個角色同時運行到一個目標，如無有效的演算法讓彼此以合適方式避開這個游戲效果是非常差的，常用的演算法有如Flocking演算法，用合力的方式計算朝向與速度，將角色分為三個基本的行為：聚集，分散，列隊 去解決，這一演算法用的非常廣；更加復雜的演算法如RVO演算法。 4。一些移動行為演算法。如：追趕，逃避，插入，避開牆等等。 再次點下開頭：AI的實現是個非常復雜的過程，不止是演算法上的，後期各項數值的調試迭代磨合是非常需要耐心的，以上4點是很基本需要掌握解決的方面。 純手打，希望對你有幫助。

② 求視頻處理方面的英文文獻，有對照中文翻譯者為佳

高速視頻處理系統中的信號完整性分析

摘要：結合高速DSP圖像處理系統討論了高速數字電路中的信號完整性問題，分析了系統中信號反射、串擾、地彈等現象破壞信號完整性的原因，通過先進IS工具的輔助設計，找出了確保系統信號完整性的具體方法。

關鍵詞：高速電路設計 信號完整性 DSP系統

深亞微米工藝在IC設計中的使用使得晶元的集成規模更大、體積越來越小、引腳數越來越多；由於近年來IC工藝的發展，使得其速度越來越高。從而，使得信號完整性問題引起電子設計者廣泛關注。

在視頻處理系統中，多維並行輸入輸出信號的頻率一般都在百兆赫茲以上，而且對時序的要求也非常嚴格。本文以DSP圖像處理系統為背景，對信號完整性進行准確的理論分析，對信號完整性涉及的典型問題[1]——不確定狀態、傳輸線效應、反射、串擾、地彈等進行深入研究，並且從實際系統入手，利用IS模擬軟體尋找有效的途徑，解決系統的信號完整性問題。

1 系統簡介

為了提高演算法效率，實時處理圖像信息，本圖像處理系統是基於DSP+FPGA結構設計的。系統由SAA7111A視頻解碼器、TI公司的TMS320C6701 DSP、Altera公司的EPlK50QC208 FPGA、PCI9054 PCI介面控制器以及SBRAM、SDRAM、FIFO、FLASH等構成。FPGA是整個系統的時序控制中心和數據交換的橋梁，而且能夠對圖像數據實現快速底層處理。DSP是整個系統實時處理高級演算法的核心器件。系統結構框圖如圖1所示。

在整個系統中，PCB電路板的面積僅為15cm×l5cm，系統時鍾頻率高達167MHz，時鍾沿時間為0．6ns。由於系統具有快斜率瞬變和極高的工作頻率以及很大的電路密度，使得如何處理高速信號問題成為一個制約設計成功的關鍵因素。

2 系統中信號完整性問題及解決方案

2．1 信號完整性問題產生機理

信號的完整性是指信號通過物理電路傳輸後，信號接收端看到的波形與信號發送端發送的波形在容許的誤差范圍內保持一致，並且空間鄰近的傳輸信號間的相互影響也在容許的范圍之內。因此，信號完整性分析的主要目標是保證高速數字信號可靠的傳輸。實際信號總是存在電壓的波動，如圖2所示。在A、B兩點由於過沖和振鈴[2]的存在使信號振幅落入陰影部分的不確定區，可能會導致錯誤的邏輯電平發生。匯流排信號傳輸的情況更加復雜，任何一個信號發生相位上的超前或滯後都可能使匯流排上數據出錯，如圖3所示。圖中，CLK為時鍾信號，D0、D1、D2、D3是數據匯流排上的信號，系統允許信號最大的建立時間[1]為△t。在正常情況下，D0、D1、D2、D3信號建立時間△t1<△t，在△t時刻之後數據匯流排的數據已穩定，系統可以從匯流排上采樣到正確的數據，如圖3(a)所示。相反，當信號D1、D2、D3受過沖和振鈴等信號完整問題干擾時，匯流排信號就發生了相位偏移和失真現象，使D0、D1、D2、D3信號建立時間△t2>△t，系統在△t時刻將從匯流排上得到錯誤數據信息，產生錯誤的控制信號，擾亂了正常工作，使信號完整性問題更加復雜，如圖3(b)所示。

2．2 信號的反射

信號的反射就是指在傳輸線端點上有回波。當傳輸線上的阻抗不連續時，就會導致信號反射的發生。在這里，以圖4所示的理想傳輸線模型來分析與信號反射有關的重要參數。圖中，理想傳輸線L被內阻為Ro的數字信號驅動源Vs驅動，傳輸線的特性阻抗為Zo，負載阻抗為RL。在臨界阻抗情況下，Ro＝Zo=RL，傳輸線的阻抗是連續的，不會發生任何反射。在實際系統中由於臨界阻尼情況很難滿足，所以最可靠的適用方式是輕微的過阻尼，因為這種情況沒有能量反射回源端。

負載端阻抗與傳輸線阻抗不匹配會在負載端(B點)反射一部分信號回源端(A點)，反射電壓信號的幅值由負載反射系數幾決定，可由下式求出：

PL=(RL-Z0)/(RL+Z0) (1)

式中，PL稱為負載電壓反射系數，它實際上是反射電壓與入射電壓之比。由式(1)可知—1≤PL≤+1，當RL=Zo時，PL＝0，不會發生反射。可見，只要根據傳輸線的特性阻抗進行終端匹配，就能消除反射。從原理上說，反射波的幅度可以大到入射電壓的幅度，極性可正可負。當RL<Zo時，PL<0，處於過阻尼狀態，反射波極性為負；當RL>Zo時，PL>0，處於欠阻尼狀態，反射波極性為正。當從負載端反射回的電壓到達源端時，又將再次反射回負載端，形成二次反射波，此時反射電壓的幅值由源反射系數PS決定，可由下式求出：

Ps=(R0-Zo)/(R0+Z0) (2)

在高速數字系統中，傳輸線的長度符合下式時應使用端接技術：

L>tr/(2tpdl) (3)

式中，L為傳輸線線長，tr為源端信號的上升時間，tpdL為傳輸線上每單位長度的帶載傳輸延遲。即當tr小於2TD(TD為傳輸延時)時，源端完整的電平轉移將發生在從傳輸線的接收端反射回源端的反射波到達源端之前，這需要使用端接匹配技術，否則會在傳輸線上引起振鈴。

結合圖1設計本系統時，採用MentorGraphics公司的信號完整性分析工具InterconnectSynthesis(IS)，信號驅動器和接收器均使用TTL_S工藝器件的IBIS模型進行電路模擬，選擇出正確的布線策略和端接方式。DSP與SBSRAM介面的時鍾高達167MHz，時鍾傳輸和延時極小，很容易在信號線出現反射現象。根據公式(2)，要消除源端的反射波必須在源端進行阻抗匹配，使反射系數PS為0。用interconnectSynthsis模擬測試可得此時鍾線的傳輸阻抗Zo=47Ω。因此，在DSP的SDCLK時鍾的輸出端應採用串聯匹配法[1][3]，串入47Ω的電阻進行源端匹配消除源端的信號反射現象。對於負載端的反射，根據公式(1)，要使PL＝0，必須保證負載阻抗RL＝Zo。因此，在SBSRAM的時鍾輸入埠應採用戴維南終端匹配法[1][3]，並聯兩個電阻R1和R2且R1＝R2=94Ω(R1//R2＝Zo)實現終端匹配，其端接前後InterconnectSynthesis模擬的波形如圖5所示。端接後信號線的反射雜訊明顯減小，滿足了系統對時鍾信號完整性的要求。

2．3 信號的串擾

串擾是指當信號在傳輸線上傳播時，因電磁耦合對相鄰傳輸線產生不期望的電壓或電流雜訊干擾。隨著電子產品的小型化，PCB板線間距減小，串擾問題更加嚴重。

對於高速電路來說，一般都採用平板電源地層，兩導體間的串擾取決於它們的耦合電感和耦合電容[3]。在數字電路設計中，通常感性串擾要比容性串擾大，所以應重點考慮導線間的互感問題。兩導體間的感性串擾系數計算可以通過下式得出：

式中，常數k取決於信號的建立時間和信號線的干擾長度(平行長度)；H為信號線到平板地層的距離；D為兩干擾線的中心的距離。由(4)式可知，串擾大小與線間距(D)成反比，與線平行長度(K)成正比，與信號線距地層的距離(H)成正比。針對這些串擾的特性，結合圖1設計本系統時，主要用以下幾種方法減少串擾：(1)加大線的間距，盡可能減少DSP與SBSRAM、SDRAM以及FPGA之間高速信號線的平行長度，必要時採用jog方式走線；(2)高速信號線在滿足條件的情況下，加入端接匹配減少或消除反射，從而減小串擾；(3)將信號層的走線高度限制在高於地平面10mil左右，可以顯著減少串擾；(4)用InterconnectSynthsis進行模擬時，在串擾嚴重的兩條線之間插入一條地線，可以起到隔離作用，從而減少串擾。

2．4 地彈雜訊

隨著數字設備的速度變快，它們的輸出開關時間越來越少。當大量的開關電路同時由邏輯高變為邏輯低時，由於地線通過電流的能力不夠，電流涌動就會引起地參考電壓發生波動，稱之為地彈。

在地彈現象的分析中，對驅動設備來說，外部設備都被看作容性負載即(Cl～Cn)。這些容性負載儲存的電荷量Q可由下式決定：

Q＝V×C

上式中，V是電容器兩端上的電壓，C是容性負載的電容。

一個設備外界和地線通路都有內在的電感L[2]。在大量數字邏輯輸出由高電壓變為低電壓的過程中，儲存在負載電容的電荷會湧向設備地，這個電流浪涌會通過電感L產生電壓V GND，其大小可用下式得出：

VGND=L×(di/dt)

由於系統地和設備地之間的電壓VGND的存在，對於各邏輯器件來說，其有效輸入電壓值為：VACTIVE＝VIN—VGND。如果地彈產生的電壓值VGND過大，就會導致各器件對輸入電壓判斷的錯誤，擾亂整個系統的正常工作。

結合圖1設計本系統時，由於FPGA控制邏輯部分存在大量快速開關輸出電路，當這些開關電路同時發生邏輯變化時，產生的開關電流會湧入地平面迴路，破壞地平面的參考電壓，引入地彈雜訊。對於地彈雜訊的干擾，通過下面幾種方法可減小地彈對電路的影響：(1)增加VCC／GND間的去耦電容個數，並盡可能使其與Vcc／GND對數相等；(2)降低器件的輸出容性負載，減少負載器件個數；用SN74LVTH62245驅動器實現FPGA同步輸出引腳與DSP數據線的隔離；用SN74LBI6244構成地址隔離，降低同步雜訊對DSP高速電路的干擾；(3)在電源輸入端跨接10～100μF的電解電容，在每個集成電路晶元都布置一個O．1μF的瓷片電容，濾掉電源和地的雜訊信號；(4)對於抗噪能力弱、關斷時電源變化大的SBSRAM、SDRAM存儲器件，在晶元的電源線和地線之間接入0．1μF的退耦電容。在採取地彈雜訊處理後利用頻譜分析儀測得系統的騷擾頻譜，可以發現頻譜已經變得很平坦，騷擾電平已降到系統容許的范圍以內，達到了系統對地參考電壓的要求。

在高速電路設計中，信號完整性問題是一個復雜的問題，往往有許多難以預料的因素影響整個系統的性能。因此信號完整性分析在高速電路設計中的作用舉足輕重，只有解決好高速設計中的信號完整性問題，高速系統才能准確、穩定地工作。

High-speed video processing system of signal integrity analysis

Abstract: combining the high-speed DSP image processing system, discusses the high-speed digital circuit, signal integrity, analyzes the problems in the system of signal reflections, ground, such phenomena as the signal integrity, destroyed by advanced design, the auxiliary tool IS found to ensure the integrity of the specific method of signal system.

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Keywords: high-speed circuit design signal integrity DSP system

Deep submicron process in IC design makes the use of chip integrated larger, more and more small volume, pin number more, Due to the recent development of IC technology, make its speed is getting higher and higher. Thus, makes the signal integrity problems caused extensive concern of electronic designers.

In video processing system, input and output signal of multidimensional parallel commonly in frequency over 100 MHZ of timing requirements, but also very strictly. Based on DSP image processing system for signal integrity as the background, theoretical analysis, the accurate signal integrity of typical problems involved in [1], uncertainty, transmission and reflection, the effect of ground, etc, and in-depth study from actual system by simulation software, IS looking for effective ways to solve the system, signal integrity problem.

1 system

In order to improve the efficiency of the algorithm, the real-time image information, the image processing system is based on DSP + FPGA design. Video codecs, SAA7111A system consists of TI company TMS320C6701 DSP, Altera company EPlK50QC208 FPGA, PCI9054 PCI interface controller and SBRAM, SDRAM, FIFO, FLASH, etc. The whole system is the FPGA sequential control center and data exchange, and able to bridge of image data quickly. DSP is the system of the core real-time senior algorithm. System structure diagram is shown in figure 1.

In the system, PCB for 15cm l5cm x only, the system clock frequency clock time, as 167MHz along 0.6 ns. Due to the system has the high slope fast transient and the working frequency and great circuit, how to deal with high density restriction design problem becomes a signal is the key factor to success.

2 system signal integrity problems and solutions

2.1 signal integrity problem generating mechanism

Signal integrity refers to the signal transmission through physical circuit, signal waveform and the receiver to see the sender sends signal waveform in error range, and spatial adjacent signals interactions are permitted scope. Therefore, the signal integrity analysis of the main target is the reliable guarantee high speed digital signal transmission. Actual signal voltage fluctuation, there is always shown in figure 2. In A and B two e to overshoot and ringing [2] to signal amplitude into the shaded part of uncertainty, may cause errors logic level. Bus signal transmission of the situation is more complex, any signal on the phase lag could advance or data error on the bus, as shown in figure 3 below. In the diagram, as the clock signal, D0 CLK, D1, D2, D3 is the data bus signals, systems allow the maximum signal established time [1] for the train. In normal circumstances, D0, D1, D2, build time signal D3 t1 < train and train in the train t moments after the data stability data bus, the system can from the bus to the correct data sampling, as shown in figure 3 (a). Conversely, when the signal D1, D2, ecated and ringing D3 signal integrity, bus signal interference problems occurred in phase offset and distortion, make D0, D1, D2, build time train t2 D3 signal system in > train t t will train from the bus get error data, the control signal, disturbed the normal work, make the signal integrity problem is more complex, as shown in figure 3 (b).

The reflected signals 2.2

The reflected signals in line with echo endpoint. When the transmission line impedance discontinuity, will cause the signal reflections. Here, in the ideal 4 transmission model to analysis and reflection signals about the important parameters. In the figure, the ideal transmission by resistance for the Ro L digital signal source driver drive, the transmission Vs the characteristic impedance Zo, load impedance for for RL. In critical impedance Zo circumstance, Ro = = RL, transmission impedance is continuous, won't proce any reflection. In the actual system can not meet the conditions e to critical damping, so the most reliable applicable way is slightly over damping, because this is not the source of energy reflected back.

The load impedance and transmission impedance mismatch in the load (B) of the source signal reflected back (points), reflected voltage signal amplitude of reflection coefficient of load, under A decision by A type:

PL = (RL - Z0) / (RL + Z0) (1)

Type, PL called load voltage reflection coefficient, it is actually reflected voltage and the incidence of voltage. By type (1) known - 1 + 1, than PL acuities when RL = Zo, PL = 0, won't happen. Visible, according to the characteristics of transmission impedance terminal matching, we can eliminate reflected. From the theory of reflection wave amplitude, said to the incident voltage can be, which negative polarities. When RL < < 0 Zo, PL, in the state of damping, had reflected wave polarity is negative, When RL > > 0 Zo, PL, in the state of reflection wave damping, for polarity. When the load reflected back from the client to the source voltage, and will again reflected back to load, formed secondary reflected wave, reflected voltage amplitude of the source of reflection coefficient decided by the next, PS of a type:

Ps = (R0 - Zo) / (R0 + Z0) (2)

In high speed digital systems, the length of the transmission line should be used when the next type with technology:

L > tr / (2tpdl) (3)

Type, L for transmission/long tr is the source, the rise time of signal transmission line, tpdL per unit length for carrying the belt transmission delay. When 2TD < tr (TD for transmission delay), the complete source of multilevel transfer will occur in the transmission from the source end receiver reflected back to the reflection wave source, the need to use before termination matching technology, otherwise it will cause ringing in the transmission line.

Combined with the system design of figure 1, MentorGraphics using the signal integrity analysis tools Co., InterconnectSynthesis (IS), signal receiver using drivers and TTL_S craft device IBIS model simulation, choose the correct wiring strategy and termination methods. DSP and SBSRAM interface as the clock 167MHz, clock and delay in tiny, easily reflected signal. According to the formula (2), to eliminate the reflected wave source in the source end must be on impedance matching, make the reflection coefficients for 0. PS. With interconnectSynthsis simulation test can the clock line transmission impedance Zo = 47 Ω. Therefore, in SDCLK DSP clock output should adopt series matching method [1], [3], string into Ω 47 on the resistance of the signal source to eliminate reflected. According to the reflection, load formula (1), to make PL = 0, must guarantee load impedance Zo RL =. Therefore, in SBSRAM clock input should adopt the terminal matching method [1], [3], parallel two resistance R1 and R2 and R1 = R2 = 94 Ω (R1 / / R2 = Zo), JiDuan before termination matches up InterconnectSynthesis simulation of the waveform as shown in figure 5. After the termination of the reflected signal noise, to meet the system clock signal integrity.

The signal of 2.3

Crosstalk refers to spread in line when signal by electromagnetic coupling, adjacent to proce unexpected transmission line voltage or current noise interference. As the miniaturization of electronic procts, PCB line spacing, crosstalk problem is more serious.

For high-speed circuits, usually by power between the two conctors formation, depending on their cross coupling capacitance and inctance coupling [3]. In the digital circuit design, usually perceptual link to hematocrit of sex, so shall consider the mutual inctance between the wires. Between two conctors of calculating coefficients of sensibility next type that can be through:

Type, constant k depends on the establishment of the signal and the disturbance signal length (parallel length), H for signal to the distance; flat strata, D for two interference lines of center distance. By (4) type, size and cross line spacing (D), and inversely proportional to parallel length (K) is proportional to the distance from the strata signal proportional to the (H). According to these characteristics, the combination of the system design of figure 1, mainly in the following methods of recing (1) increasing line spacing, minimize DSP and SBSRAM, SDRAM between signal and FPGA, high-speed parallel length by jog means necessary wiring, (2) high signal on the circumstances, join termination matches to rece or eliminate reflected, thus rece crosstalk, (3) will signal lines layer above ground height in 10mil around, can significantly rece crosstalk, (4) InterconnectSynthsis using simulation, the serious in crosstalk between two lines, can rise to insert wire isolation effects, thereby recing the crosstalk.

2.4 ground noise

Along with the digital equipment faster, their output switch with less and less time. When a switch circuit by logic high into a logical low, because of the ground through the current capacity, the current surge will not happen to a reference voltage fluctuation caused, call to play.

In the analysis, the phenomenon of elastic to drive equipment, external devices are regarded as capacitive loads namely (Cl ~ Cn). The capacitive loads can be stored charge quantity Q: by next type

Q = V x C

The type of capacitor, V is in the voltage, C are capacitive loads of capacitance.

A device outside and ground pathways are inherent inctance L [2]. In large Numbers of high voltage output logic to low voltage, the process of load capacitance stored in charge will be flocking to the electric equipment, stray inctance L proced by surge voltage GND V, its size, type used under

VGND = L x (di/dt)

Due to the system and equipment to the voltage between VGND, for each logical device, the effective input voltage values for VACTIVE = VIN - VGND:. If the voltage proced to play VGND too, can cause various components of the input voltage error of judgment and disrupt the normal work of the whole system.

Combined with the system design of figure 1, because the FPGA control logic part a quick switch output circuit, when the switch logic circuit occur at the same time, the switch currents generated into the ground plane loop, will destroy the ground plane, introction to play a reference voltage noise. To play for the noise, through the following method can rece the influence of the circuit to play: (1) the increase of the VCC/GND decoupling capacitor, and as far as possible the number with the VCC/GND logarithmic equal, (2) rece the output devices, rece the capacitive loads load device number, SN74LVTH62245 drive with FPGA realizing synchronization output pin data with DSP isolation, With SN74LBI6244 constitute the address, lower noise high-speed circuits of DSP synchronization of interference, (3) in the power input jumper 10 ~ 100 mu F the electrolytic capacitor, in every integrated circuit chips are decorated a o. 1 F ceramic capacitors, close to filter out the noise signal and power, (4) for antinoise ability weak, shut off the power supply when the big change, SDRAM storage devices, SBSRAM in chip power and ground between 0.1 muon F of access decoupling capacitors. In the ground to handle by spectrum analyzer after noise measurement system of harassment can be found, frequency spectrum has become very smooth, harassing level has dropped for system within the reach of voltage reference system.

In high-speed circuit design, the signal integrity problem is a complex problem, often have many uncertain factors affect the performance of the system. Therefore signal integrity analysis in high-speed circuit design, the only solution plays an important role in the design of high-speed signal integrity, high-speed system can accurately, steady job.

③ 即時戰略游戲中實用的尋路演算法都有哪些

Potential Field，它是將地圖用一個矩陣來表示，矩陣儲存著大小不同的電勢（整數）。例如，正電勢表示吸引，負電勢表示排斥。而游戲中的單位本身是一個負電勢，游戲以一個數組儲存所有單位的電勢和位置。這樣，在計算一個單位需要怎麼從A點到B點時，我們可以用一個新的矩陣將目的地B點設成正電勢，並以不同方式（如圓形、四邊形等）輻射開來，離B點越遠電勢越低，直到0。然後將地圖矩陣，目的地矩陣，和所有單位數組的電勢相加，得出一個新的、反映當前游戲世界的電勢矩陣，然後單位再選擇周圍所有電勢點中的最高電勢點去走。不過這里坑很多，因為它本質上是Greedy Algorithm，所以它未必能找出解。然而在某些設定中，例如在沒有過於復雜地形，並且需要單位自動不相互覆蓋的情況下，Potential Field還是可以完成任務。

Flocking Behavior，在對於一大群單位的尋路，計算量是很大的，而且往往會有很多的重復，這些都是可以避免的。如果單位的移動是利用Steering Behavior來實現的話，那麼就可以為其中一個單位，稱之為Leader，計算路徑（例如用導航網格），然後其他單位按照以下Flocking原則來移動：1. 分離，避開相鄰單位2. 一致，和整體的移動方向一致，這里應該是Leader的移動方向3. 聚合，向整體的平均位置靠攏這樣的話，就可以降低尋路的計算量，並且得到更加真實的群體單位行進效果。

④ Unity3D做一個手游怪物AI,需要掌握什麼

ai是個復雜的實現。
1。狀態轉換。例如被攻擊後轉向敵人，釋放魔法後進去休息狀態，敵人過於強大ai會逃跑，這些問題首先直觀的使用if else語句，可以這樣的ai通常非常難以寫出來，而且ai的修改會很麻煩，這時候業內慣用「有限狀態機」解決此問題。
2。路徑規劃。怎樣從A點到B點要繞過中間的障礙物，這需要演算法解決，非常成熟的解決方案就是 A＊尋路（A星尋路演算法），這中演算法適合解決固定障礙的路徑規劃，如繞過山，河，溝不可移動的障礙。另外點下更復雜的戰術式尋路，如避開敵人火力區的路線，避開地面雷達的飛行路線等。
3。避開障礙物體。其實這也屬於「路徑規劃」類的問題，只不過此問題解決的是動態的障礙，和上面的第2點有非常大的區別。如20或者200個角色同時運行到一個目標，如無有效的演算法讓彼此以合適方式避開這個游戲效果是非常差的，常用的演算法有如Flocking演算法，用合力的方式計算朝向與速度，將角色分為三個基本的行為：聚集，分散，列隊 去解決，這一演算法用的非常廣；更加復雜的演算法如RVO演算法。
4。一些移動行為演算法。如：追趕，逃避，插入，避開牆等等。
再次點下開頭：AI的實現是個非常復雜的過程，不止是演算法上的，後期各項數值的調試迭代磨合是非常需要耐心的，以上4點是很基本需要掌握解決的方面。
純手打，希望對你有幫助。

⑤ 如何用隊列控制怪物一個一個銷毀 unity

ai是個復雜的實現。1。狀態轉換。例如被攻擊後轉向敵人，釋放魔法後進去休息狀態，敵人過於強大ai會逃跑，這些問題首先直觀的使用ifelse語句，可以這樣的ai通常非常難以寫出來，而且ai的修改會很麻煩，這時候業內慣用「有限狀態機」解決此問題。2。路徑規劃。怎樣從A點到B點要繞過中間的障礙物，這需要演算法解決，非常成熟的解決方案就是A＊尋路（A星尋路演算法），這中演算法適合解決固定障礙的路徑規劃，如繞過山，河，溝不可移動的障礙。另外點下更復雜的戰術式尋路，如避開敵人火力區的路線，避開地面雷達的飛行路線等。3。避開障礙物體。其實這也屬於「路徑規劃」類的問題，只不過此問題解決的是動態的障礙，和上面的第2點有非常大的區別。如20或者200個角色同時運行到一個目標，如無有效的演算法讓彼此以合適方式避開這個游戲效果是非常差的，常用的演算法有如Flocking演算法，用合力的方式計算朝向與速度，將角色分為三個基本的行為：聚集，分散，列隊去解決，這一演算法用的非常廣；更加復雜的演算法如RVO演算法。4。一些移動行為演算法。如：追趕，逃避，插入，避開牆等等。再次點下開頭：AI的實現是個非常復雜的過程，不止是演算法上的，後期各項數值的調試迭代磨合是非常需要耐心的，以上4點是很基本需要掌握解決的方面。純手打，希望對你有幫助。