A. 跪求基於51單片機數字時鍾的外文文獻，不是單片機外文翻譯，謝謝各位啊
哇哈，外文啊，我不知道到底有幾個單片機教授精通英文。中國像沒什麼人同時精通英文跟單片機。你還是用翻譯軟體去一句一句翻譯。以前我的摘要都是這么乾的。不然你只能去圖書館找了。圖書館我覺得還未必有時鍾這么初級設計的論文。
B. 單片機 LED 外文翻譯
China started to use MCU is in 1982, the 1990 s of single chip microcomputer and market is developing very fast. In recent years, the single chip has become a powerful tool in the field of science and technology, human social life right-hand man. It is widely used, and not only embodies in instrial control, mechanical and electrical application, intelligent instrument, real-time control, aviation, sophisticated weapons instries and areas of intelligence, and of high precision, and in human daily life also can be seen everywhere it figure. The washing machine, freezer, electronic toys, radio and other home appliances match on single chip microcomputer, not only improve the level of intelligence, enhance the function, also make the human life more convenient, comfortable, rich and colorful. After the 1990 s, the embedded System design by embedded microcontroller processor with the core of integrated circuit "class design, graally turned to" integration System "class design, in MCU (Micro Controller Unit) put forward the System Chip SoC (System on a Chip) of the basic concepts, for example,
C. 機械類畢業論文的下載網址,要免費的才可以.
機械類畢業設計類資料你可以網路搜索一下九愛圖紙或者9icad，網站裡面有上萬機械圖紙和上千套機械畢業設計（圖紙+說明書），相信這些資料對你做畢業設計一定會有幫助的。
D. 求一篇畢業論文外文翻譯原文
你是要翻譯成外文。還是外文翻譯成中文。
E. 單片機英文文獻及翻譯，2200字左右
Single-Chip Microcomputer
有的時候，也可以用SingleChip來代替
下面鏈接的第六章有講單片機Single Chip Microcmputer 第148頁開始
http://books.google.co.nz/books?id=AUtTx3TgO7IC&pg=PT41&lpg=PT41&dq=what+is+Single+Chip+Microcomputer&source=web&ots=QQqVentmyy&sig=ZPBVtVXwiQakAtCIXJqzRw_BobE&hl=en&sa=X&oi=book_result&resnum=8&ct=result#PPT41,M1
這是一段中漢對照的。
中文:
單片機是把主要計算機功能部件都集成在一塊晶元上的微型計算機。它是一種集計數和多中介面於一體的微控制器，被廣泛應用在智能產品和工業自動化上，而51單片機是個單片機中最為典型和最有代表性的一種。
本課題選擇89S51為核心控制元件，設計了一個日常生活中用到的電子音樂門鈴系統。當功能按鍵按下，音樂響起，發光二極體隨著音樂的節拍進行閃爍，LED顯示相應的定時器初值。音樂演奏過程中再次按下按鍵無效，只有當音樂段結束再次按下才有效。如果是電子音樂門鈴在響，按下復位按鍵就終止，顯示初始狀態。經過實踐證明，本系統運行穩定，具有一定的實用價值。
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翻譯:
SCM is a major piece of computer components are integrated into the chip micro-computer. It is a multi-interface and counting on the micro-controller integration, and intelligence procts are widely used in instrial automation. and MCS-51 microcontroller is a typical and representative.
The topics chosen for the 89S51 control of the core components used in the design of a daily electronic music doorbell system. When the function button is pressed, the music sounded and the music beats with light emitting diodes for flickered. Initial corresponding LED timer. Musical process again pressed the button ineffective, and only when pressed again before the end of the music effectively. If the doorbell ring for electronic music, press the button on the rection and termination, showed initial state. Practice has proved that the system is stable and has some practical value.
本設計是以凌陽16位單片機為重心，介紹語音控制在機械手中的應用，實現微型舵機的運作，完成所指定的動作。其中通過凌陽16位單片機輸出的脈沖信號來准確的控制機械手的擺動角度，機械手的捏拿動作由電磁鐵完成，電磁鐵的通斷由凌陽16位單片機的I/O口控制，硬體和軟體都在具體的實驗中證明了其可行性
This design is take insults the positive 16 monolithic integrated circuits as a center of gravity, introced the pronunciation control in manipulator's application, the realization miniature servo operation, completes the movement which assigns. Through insults the pulse signal which the positive 16 monolithic integrated circuits outputs to come the accurate control manipulator to swing the angle, the manipulator pinches takes the movement to complete by the electro-magnet, the electro-magnet passes the legal reason for judgment to insult the positive 16 monolithic integrated circuits I/O control, the hardware and the software all have proven its feasibility in the concrete experiment
F. 急急急！！！畢業設計啊，電子萬年歷外文翻譯。
呵呵……樓下的有點理，這個一般很難找，要手工翻譯的
G. 求一篇關於 基於51單片機的電子琴設計 的外文，有翻譯最好了。。謝謝
找個語音晶元就行了
H. 急急急急！！！單片機外文翻譯
單片機論文
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文:admin 發表時間2008-9-26 11:29:00
單片機論文：單片機是一種嵌入式系統模擬方法，通過一種特殊設計的指令集模擬器ISS將軟體調試器軟體Keil uVision2和硬體語言模擬器軟體Modelsim連接起來，實現了軟體和硬體的同步模擬。
關鍵詞：BFM，TCL，Verilog，Vhdl，PLI，Modelsim，Keil uVision2，ISS，TFTP，HTTP，虛擬網卡，Sniffer，SMART MEDIA，DMA，MAC，SRAM，CPLD
縮略詞解釋：
BFM：匯流排功能模塊。在HDL硬體語言模擬中，BFM完成抽象描述數據和具體的時序信號之間的轉換。
PLI：Verilog編程語言介面，是C語言模塊和Verilog語言模塊之間交換數據的介面定義。
TCL：字面意思是工具命令語言，是一種解釋執行語言，流行EDA軟體一般都集成有TCL。使用TCL用戶可以編寫控制EDA工具的腳本程序，實現工具操作自動化。
ISS：CPU指令集模擬器，可以執行CPU的機器碼。
TFTP：簡單文件傳輸協議，Windows的tftp.exe既是該協議的客戶端實現。
SMART MEDIA：一種存儲卡，常用於數碼相機、MP3。
DMA：直接內存訪問。用於外部設備之間高速數據轉移。
MAC：媒體接入控制器。本文中是指網卡晶元。
前言
傳統的嵌入式系統中，設計周期、硬體和軟體的開發是分開進行的，並在硬體完成後才將系統集成在一起，很多情況下，硬體完成後才開始進行實時軟體和整體調試。軟硬體聯合模擬是一種在物理原型可用前，能盡早開始調試程序的技術。
軟硬體聯合模擬有可能使軟體設計工程師在設計早期著手調試，而採用傳統的方法，設計工程師直到硬體設計完成才能進行除錯處理。有些軟體可在沒有硬體支持的情況下完成任務的編碼，如不涉及到硬體的演算法。與硬體相互作用的編碼在獲得硬體之前編寫，但只有在硬體上運行後，才能真正對編碼進行調試。通過採用軟硬體聯合模擬技術，可在設計早期開始這一設計調試過程。由於軟體的開發通常在系統開發的後段完成，在設計周期中較早的開始調試有可能將使這一項目提早完成，該技術會降低首次將硬體和軟體連接在一起時出現意外而致使項目延期完成所造成的風險。
在取得物理原型前，採用軟硬體聯合模擬技術對硬體和軟體之間的介面進行驗證，將使你不會花太多的時間在後期系統調試上。當你確實拿到物理原型開始在上面跑軟體的時候，你會發現經過測試的軟體部分將會正常工作，這會節省項目後期的大量時間及努力。
軟硬體聯合模擬系統由一個硬體執行環境和一個軟體執行環境組成，通常軟體環境和硬體環境都有自己的除錯和控制界面，軟體通過一系列由處理器啟動的匯流排周期與硬體的交互作用。本文以一個Mini Web卡的開發介紹一種軟硬體聯合模擬系統。
該方案的核心是採用一個51單片機模擬引擎GoldBull ISS51（以下簡稱ISS51），ISS51是51單片機開發環境Keil uVision2的一個插件，ISS51具有連接Keil和硬體模擬環境Modelsim的介面，可以實現軟硬體同步模擬。在該系統中，Keil作為軟體調試界面，Modelsim作為硬體模擬和調試界面，ISS51負責軟體執行、監控軟體斷點、單步執行、內存和寄存器數據返回給Keil、CPU匯流排時序產生和捕獲、內部功能模塊（如定時器，串口）的運行等功能。
Mini Web卡介紹
Mini Web卡是一個運行在單片機上的Web伺服器，提供網口連接，有大容量文件系統，提供TFTP和HTTP服務。盡管軟體系統比較復雜，但優化編譯後，執行代碼還不足25K，為後續升級留下了足夠空間。51CPU採用SST89系列，這種CPU具有ISP功能，可以通過RS232串口，直接將目標碼下載到CPU。
DMA控制邏輯是一個可編程邏輯器件，採用的是ALTERA的CPLD EPM240，主要功能是實現外圍器件之間的DMA傳遞。因為51CPU進行IO訪問是很低效的，需要24個時鍾周期才能進行一次IO訪問，在外圍設備之間轉移數據則需要更多的時鍾周期，使用DMA控制邏輯可以達到3個時鍾周期就能轉移一個位元組。本系統中處理多種網路協議，需要大量報文收發和文件系統訪問，採用DMA可以極大地提高51單片機的數據處理速度。DMA通道主要有MAC晶元與RAM之間的數據塊轉移，SMART MEDIA和RAM之間的數據塊轉移。
網卡晶元採用的是AX88796，主要的優點是可以和51CPU方便地介面；支持100M乙太網，速度高；有較大的接收報文緩存，能夠平滑網路流量，減少因51CPU處理速度慢導致的報文丟棄和重發。
SMART MEDIA是一個移動存儲卡，主要用於存儲文件，Mini Web卡支持8M到256M的SMD卡。
文件系統是Mini Web卡的新開發模塊，文件系統的測試主要通過TFTP來進行，為此Mini Web卡上的TFTP服務程序進行了特殊設計，支持格式化SMART MEDIA，獲取剩餘空間，獲取文件名列表，上傳、下載和刪除文件。
軟硬體聯合模擬的必要性：
Mini Web卡軟體模塊多，軟體開發風險較大。軟體對硬體的依賴較強，FLASH存儲器的訪問驅動、網卡驅動、DMA驅動，需要軟硬體協同調試。
文件系統的開發，在模擬環境下更容易和快捷。比如在模擬結束時，可以將SMART MEDIA模擬模型中的數據倒換到磁碟文件中，在模擬開始時，將磁碟文件中的數據載入到SMART MEDIA模擬模型中，在定位文件系統的問題時，這一個功能很有用。
採用軟硬體聯合模擬，便於系統前期設計。51單片機的外部RAM訪問效率較低，內存拷貝、外部器件之間的數據塊轉移很浪費時間。將大量數據的拷貝操作或數據塊校驗、比較操作在CPLD內實現，可以大大改進51單片機處理數據的能力。通過軟硬體聯合模擬，可以評估CPLD處理數據對性能的改進。
Mini Web卡軟硬體聯合模擬系統：
軟硬體聯合模擬主要解決的問題是系統功能設計與驗證
，它不解決電源、濾波電容、匯流排電平兼容問題。
做系統模擬，首先要對硬體系統建模。我們關注的是系統設計的正確性和可執行性。
系統中的串口只是用來支持ISP下載軟體，軟體部分沒有對串口做任何操作，所以系統模擬可以不必考慮。
網卡晶元AX88796，廠商沒有提供模擬模型。它與CPU的介面符合ISA介面標准，軟體對AX88796的操作是根據NE2000標准網卡晶元設計的，由此我們建立了一個網卡晶元的模擬模型。我們設計了一個MAC BFM來模擬網卡晶元的ISA介面，NE2000定義的寄存器在C模型中實現，MAC BFM與NE2000寄存器C模型通過PLI接****換數據。
SRAM模擬模型是很容易獲取的，很多器件生產商都提供Verilog模擬模型，但器件生產商提供的Verilog模擬模型都包含復雜的延時控制代碼，這會影響模擬速度。根據經驗，我們可以確保SRAM在單板設計中被正確應用，不會產生時序問題，所以我們可以採用一個簡化的SRAM模擬模型，這是我們自己設計的，有效代碼只有十幾行。
51CPU BFM 負責單片機管腳時序的產生和捕獲。51CPU BFM是與ISS51緊密捆綁的，由ISS51安裝SMART MEDIA是三星公司提供的模擬模型，我們使用的也是三星公司的同類型存儲卡。該模型可以用於驗證軟體操作SMART MEDIA的正確性和DMA Controller的介面時序。
DMA Controller是Mini Web卡硬體開發的一部分，將邏輯設計代碼應用於模擬，既能檢測邏輯設計的正確性，又能使整個模擬系統得以正常運轉。
將上述硬體模型連接起來，產生下圖所示硬體系統模型圖：
圖2. Mini Web卡硬體模塊電路圖
圖2中U11為SMART MEDIA模擬模型，U4為DMA Controller模型。
虛擬網卡
做系統模擬，必須輸入來自真實世界的激勵，並將模擬系統的輸出傳遞到真實世界。即便是不能連接到真實世界，也應該提供模擬真實世界的輸入，並對模擬系統的輸出進行檢測和分析。
對於Mini Web卡來說，它和真實環境是通過網口連接的。使用虛擬網卡技術，能夠將圖3中的MAC C Model與虛擬網卡進行通訊。
對於運行在Windows系統上的應用程序來說，它並不知道網卡是虛擬的還是真實的，應用程序通過虛擬網卡收發數據，事實上是與模擬系統在進行網路通信。
這樣就可以使用TFTP向Mini Web卡模擬系統傳遞網頁文件，使用IE瀏覽Mini Web卡模擬系統中的網頁，Mini Web卡的所有功能都能夠被檢驗。
使用網路臭探器Sniffer可以監控虛擬網卡的報文流，方便協議調試。
模擬加速技術
軟硬體聯合模擬，影響模擬速度的瓶頸在HDL代碼部分的模擬。如果不設法提高HDL代碼部分的模擬速度，軟體調試就非常低效。
提高硬體模擬速度的方法之一是軟體硬體模擬採用事件同步，只在CPU訪問IO時保持軟體和硬體是同步的。
模擬加速方法之二是硬體模擬系統時鍾休眠。對於Mini Web卡來說，只有DMA Controller是受時鍾控制的，軟體沒有操作DMA Controller的期間，DMA Controller的運作是毫無意義的，所以可以在非DMA操作期間，對時鍾進行休眠；ISS51在每次IO訪問時，給出與上次IO訪問的時間差，這個時間差經過處理可以作為時鍾休眠的時間段。如果ISS51連續進行IO訪問，就不會產生時鍾休眠了。DMA Controller工作於查詢方式，可以採用時鍾休眠技術，而不會導致模擬與真實結果的不一致。方法之三是，縮短SMART MEDIA模擬模型中的一些長延時的時間參數。因為在等待SMART MEDIA進入就緒狀態時，CPU必須連續查詢IO，影響模擬速度。我們主要用於軟體功能驗證，這種修改也是可以接受的。
方法之四，在軟體設計上，謹慎使用外部中斷，因為一旦中斷啟動，ISS51需要在每個機器周期查詢是否有中斷信號，導致軟體模擬和硬體模擬在每個指令上都進行同步，影響模擬速度。如果一定要使用外部中斷，建議用C模型代替Verilog模型，這樣可不影響模擬速度；或者由用戶根據外部模塊產生外部中斷的時機，使用ISS51的控制命令，在恰當時刻使能ISS在一個普通PC （CPU為AMD速龍1000，SDRM512M 133），運行Mini Web卡模擬系統，使用PING命令測試Mini Web卡模擬系統的響應速度：
Reply from 10.10.112.76: bytes=32 time=64ms TTL=128
使用IE打開Mini Web卡模擬系統中的網頁文件，感覺和撥號上網的速度差不太多。創建多個TFTP連接，同時向模擬系統傳遞或下載網頁文件，同時使用IE進行網頁瀏覽，都無響應中斷現象出現。
總結
使用軟硬體聯合模擬，Mini Web卡不需要硬體就能進行全部功能的模擬，增強了系統設計成功的信心。軟硬體聯合模擬方便系統設計調整，可以在設計前期評估性能，方便軟體和硬體的debug，是一個值得推廣的技術。
已經發你郵箱了
I. 求51系列單片機系統實驗板的外文翻譯,大概要3000字左右
8-Bit Microcontroller-AT89C51
Features
Compatible with MCS-51 Procts
4 Kbytes of In-System Reprogrammable Flash Memory
Enrance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Mode
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel』s high density nonvolatile memory technology and is compatible with the instry standard MCS-51instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full plex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The idle Mode stops the CPU while allowing the RAM, timer/count- ers, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Configurations
Pin Description
VCC：Supply voltage.
GND：Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 may also be configured to be the multiplexed low- order address/data bus ring accesses to external program and data memory. In this mode P0 has internal pullups.
Port 0 also receives the code bytes ring Flash programming, and outputs the code bytes ring program verification. External pullups are required ring program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs.
Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes ring Flash programming and program verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pullups.
Port 2 emits the high-order address byte ring fetches from external program memory and ring accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal data memory that use 8-bit addresses (MOVX @ RI). Port 2 emits the cintents of the P2 special Function Register.
Port 2 also receives the high-order address bits and some control signals ring Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and programming verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address ring accesses to external memory. This pin is also the program pulse input (PROG) ring Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes.. Note ,however, that one ALE pulse is skipped ring each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro- gram memory. When the AT89C51is executing code from external pro- gram memory, PSEN is ac tivated twice each machine cycle, except that two PSEN activations are skipped ring each access to external data memory.
EA/VPP
External Access Enable. must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. EA should be strapped to VCC for internal program execu tions. This pin also receives the 12-volt programming enable voltage (VPP) ring Flash programming, for parts that re- quire 12-volt VPP.
XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2: Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the ty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on- chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Data Memory
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a l-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled ring S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register ring S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future procts to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers Control and status bits are contained in registers
T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers The indivial interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.