A. 跪求基于51单片机数字时钟的外文文献，不是单片机外文翻译，谢谢各位啊
哇哈，外文啊，我不知道到底有几个单片机教授精通英文。中国像没什么人同时精通英文跟单片机。你还是用翻译软件去一句一句翻译。以前我的摘要都是这么干的。不然你只能去图书馆找了。图书馆我觉得还未必有时钟这么初级设计的论文。
B. 单片机 LED 外文翻译
China started to use MCU is in 1982, the 1990 s of single chip microcomputer and market is developing very fast. In recent years, the single chip has become a powerful tool in the field of science and technology, human social life right-hand man. It is widely used, and not only embodies in instrial control, mechanical and electrical application, intelligent instrument, real-time control, aviation, sophisticated weapons instries and areas of intelligence, and of high precision, and in human daily life also can be seen everywhere it figure. The washing machine, freezer, electronic toys, radio and other home appliances match on single chip microcomputer, not only improve the level of intelligence, enhance the function, also make the human life more convenient, comfortable, rich and colorful. After the 1990 s, the embedded System design by embedded microcontroller processor with the core of integrated circuit "class design, graally turned to" integration System "class design, in MCU (Micro Controller Unit) put forward the System Chip SoC (System on a Chip) of the basic concepts, for example,
C. 机械类毕业论文的下载网址,要免费的才可以.
机械类毕业设计类资料你可以网络搜索一下九爱图纸或者9icad，网站里面有上万机械图纸和上千套机械毕业设计（图纸+说明书），相信这些资料对你做毕业设计一定会有帮助的。
D. 求一篇毕业论文外文翻译原文
你是要翻译成外文。还是外文翻译成中文。
E. 单片机英文文献及翻译，2200字左右
Single-Chip Microcomputer
有的时候，也可以用SingleChip来代替
下面链接的第六章有讲单片机Single Chip Microcmputer 第148页开始
http://books.google.co.nz/books?id=AUtTx3TgO7IC&pg=PT41&lpg=PT41&dq=what+is+Single+Chip+Microcomputer&source=web&ots=QQqVentmyy&sig=ZPBVtVXwiQakAtCIXJqzRw_BobE&hl=en&sa=X&oi=book_result&resnum=8&ct=result#PPT41,M1
这是一段中汉对照的。
中文:
单片机是把主要计算机功能部件都集成在一块芯片上的微型计算机。它是一种集计数和多中接口于一体的微控制器，被广泛应用在智能产品和工业自动化上，而51单片机是个单片机中最为典型和最有代表性的一种。
本课题选择89S51为核心控制元件，设计了一个日常生活中用到的电子音乐门铃系统。当功能按键按下，音乐响起，发光二极管随着音乐的节拍进行闪烁，LED显示相应的定时器初值。音乐演奏过程中再次按下按键无效，只有当音乐段结束再次按下才有效。如果是电子音乐门铃在响，按下复位按键就终止，显示初始状态。经过实践证明，本系统运行稳定，具有一定的实用价值。
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翻译:
SCM is a major piece of computer components are integrated into the chip micro-computer. It is a multi-interface and counting on the micro-controller integration, and intelligence procts are widely used in instrial automation. and MCS-51 microcontroller is a typical and representative.
The topics chosen for the 89S51 control of the core components used in the design of a daily electronic music doorbell system. When the function button is pressed, the music sounded and the music beats with light emitting diodes for flickered. Initial corresponding LED timer. Musical process again pressed the button ineffective, and only when pressed again before the end of the music effectively. If the doorbell ring for electronic music, press the button on the rection and termination, showed initial state. Practice has proved that the system is stable and has some practical value.
本设计是以凌阳16位单片机为重心，介绍语音控制在机械手中的应用，实现微型舵机的运作，完成所指定的动作。其中通过凌阳16位单片机输出的脉冲信号来准确的控制机械手的摆动角度，机械手的捏拿动作由电磁铁完成，电磁铁的通断由凌阳16位单片机的I/O口控制，硬件和软件都在具体的实验中证明了其可行性
This design is take insults the positive 16 monolithic integrated circuits as a center of gravity, introced the pronunciation control in manipulator's application, the realization miniature servo operation, completes the movement which assigns. Through insults the pulse signal which the positive 16 monolithic integrated circuits outputs to come the accurate control manipulator to swing the angle, the manipulator pinches takes the movement to complete by the electro-magnet, the electro-magnet passes the legal reason for judgment to insult the positive 16 monolithic integrated circuits I/O control, the hardware and the software all have proven its feasibility in the concrete experiment
F. 急急急！！！毕业设计啊，电子万年历外文翻译。
呵呵……楼下的有点理，这个一般很难找，要手工翻译的
G. 求一篇关于 基于51单片机的电子琴设计 的外文，有翻译最好了。。谢谢
找个语音芯片就行了
H. 急急急急！！！单片机外文翻译
单片机论文
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文:admin 发表时间2008-9-26 11:29:00
单片机论文：单片机是一种嵌入式系统仿真方法，通过一种特殊设计的指令集仿真器ISS将软件调试器软件Keil uVision2和硬件语言仿真器软件Modelsim连接起来，实现了软件和硬件的同步仿真。
关键词：BFM，TCL，Verilog，Vhdl，PLI，Modelsim，Keil uVision2，ISS，TFTP，HTTP，虚拟网卡，Sniffer，SMART MEDIA，DMA，MAC，SRAM，CPLD
缩略词解释：
BFM：总线功能模块。在HDL硬件语言仿真中，BFM完成抽象描述数据和具体的时序信号之间的转换。
PLI：Verilog编程语言接口，是C语言模块和Verilog语言模块之间交换数据的接口定义。
TCL：字面意思是工具命令语言，是一种解释执行语言，流行EDA软件一般都集成有TCL。使用TCL用户可以编写控制EDA工具的脚本程序，实现工具操作自动化。
ISS：CPU指令集仿真器，可以执行CPU的机器码。
TFTP：简单文件传输协议，Windows的tftp.exe既是该协议的客户端实现。
SMART MEDIA：一种存储卡，常用于数码相机、MP3。
DMA：直接内存访问。用于外部设备之间高速数据转移。
MAC：媒体接入控制器。本文中是指网卡芯片。
前言
传统的嵌入式系统中，设计周期、硬件和软件的开发是分开进行的，并在硬件完成后才将系统集成在一起，很多情况下，硬件完成后才开始进行实时软件和整体调试。软硬件联合仿真是一种在物理原型可用前，能尽早开始调试程序的技术。
软硬件联合仿真有可能使软件设计工程师在设计早期着手调试，而采用传统的方法，设计工程师直到硬件设计完成才能进行除错处理。有些软件可在没有硬件支持的情况下完成任务的编码，如不涉及到硬件的算法。与硬件相互作用的编码在获得硬件之前编写，但只有在硬件上运行后，才能真正对编码进行调试。通过采用软硬件联合仿真技术，可在设计早期开始这一设计调试过程。由于软件的开发通常在系统开发的后段完成，在设计周期中较早的开始调试有可能将使这一项目提早完成，该技术会降低首次将硬件和软件连接在一起时出现意外而致使项目延期完成所造成的风险。
在取得物理原型前，采用软硬件联合仿真技术对硬件和软件之间的接口进行验证，将使你不会花太多的时间在后期系统调试上。当你确实拿到物理原型开始在上面跑软件的时候，你会发现经过测试的软件部分将会正常工作，这会节省项目后期的大量时间及努力。
软硬件联合仿真系统由一个硬件执行环境和一个软件执行环境组成，通常软件环境和硬件环境都有自己的除错和控制界面，软件通过一系列由处理器启动的总线周期与硬件的交互作用。本文以一个Mini Web卡的开发介绍一种软硬件联合仿真系统。
该方案的核心是采用一个51单片机仿真引擎GoldBull ISS51（以下简称ISS51），ISS51是51单片机开发环境Keil uVision2的一个插件，ISS51具有连接Keil和硬件仿真环境Modelsim的接口，可以实现软硬件同步仿真。在该系统中，Keil作为软件调试界面，Modelsim作为硬件仿真和调试界面，ISS51负责软件执行、监控软件断点、单步执行、内存和寄存器数据返回给Keil、CPU总线时序产生和捕获、内部功能模块（如定时器，串口）的运行等功能。
Mini Web卡介绍
Mini Web卡是一个运行在单片机上的Web服务器，提供网口连接，有大容量文件系统，提供TFTP和HTTP服务。尽管软件系统比较复杂，但优化编译后，执行代码还不足25K，为后续升级留下了足够空间。51CPU采用SST89系列，这种CPU具有ISP功能，可以通过RS232串口，直接将目标码下载到CPU。
DMA控制逻辑是一个可编程逻辑器件，采用的是ALTERA的CPLD EPM240，主要功能是实现外围器件之间的DMA传递。因为51CPU进行IO访问是很低效的，需要24个时钟周期才能进行一次IO访问，在外围设备之间转移数据则需要更多的时钟周期，使用DMA控制逻辑可以达到3个时钟周期就能转移一个字节。本系统中处理多种网络协议，需要大量报文收发和文件系统访问，采用DMA可以极大地提高51单片机的数据处理速度。DMA通道主要有MAC芯片与RAM之间的数据块转移，SMART MEDIA和RAM之间的数据块转移。
网卡芯片采用的是AX88796，主要的优点是可以和51CPU方便地接口；支持100M以太网，速度高；有较大的接收报文缓存，能够平滑网络流量，减少因51CPU处理速度慢导致的报文丢弃和重发。
SMART MEDIA是一个移动存储卡，主要用于存储文件，Mini Web卡支持8M到256M的SMD卡。
文件系统是Mini Web卡的新开发模块，文件系统的测试主要通过TFTP来进行，为此Mini Web卡上的TFTP服务程序进行了特殊设计，支持格式化SMART MEDIA，获取剩余空间，获取文件名列表，上传、下载和删除文件。
软硬件联合仿真的必要性：
Mini Web卡软件模块多，软件开发风险较大。软件对硬件的依赖较强，FLASH存储器的访问驱动、网卡驱动、DMA驱动，需要软硬件协同调试。
文件系统的开发，在仿真环境下更容易和快捷。比如在仿真结束时，可以将SMART MEDIA仿真模型中的数据倒换到磁盘文件中，在仿真开始时，将磁盘文件中的数据加载到SMART MEDIA仿真模型中，在定位文件系统的问题时，这一个功能很有用。
采用软硬件联合仿真，便于系统前期设计。51单片机的外部RAM访问效率较低，内存拷贝、外部器件之间的数据块转移很浪费时间。将大量数据的拷贝操作或数据块校验、比较操作在CPLD内实现，可以大大改进51单片机处理数据的能力。通过软硬件联合仿真，可以评估CPLD处理数据对性能的改进。
Mini Web卡软硬件联合仿真系统：
软硬件联合仿真主要解决的问题是系统功能设计与验证
，它不解决电源、滤波电容、总线电平兼容问题。
做系统仿真，首先要对硬件系统建模。我们关注的是系统设计的正确性和可执行性。
系统中的串口只是用来支持ISP下载软件，软件部分没有对串口做任何操作，所以系统仿真可以不必考虑。
网卡芯片AX88796，厂商没有提供仿真模型。它与CPU的接口符合ISA接口标准，软件对AX88796的操作是根据NE2000标准网卡芯片设计的，由此我们建立了一个网卡芯片的仿真模型。我们设计了一个MAC BFM来仿真网卡芯片的ISA接口，NE2000定义的寄存器在C模型中实现，MAC BFM与NE2000寄存器C模型通过PLI接****换数据。
SRAM仿真模型是很容易获取的，很多器件生产商都提供Verilog仿真模型，但器件生产商提供的Verilog仿真模型都包含复杂的延时控制代码，这会影响仿真速度。根据经验，我们可以确保SRAM在单板设计中被正确应用，不会产生时序问题，所以我们可以采用一个简化的SRAM仿真模型，这是我们自己设计的，有效代码只有十几行。
51CPU BFM 负责单片机管脚时序的产生和捕获。51CPU BFM是与ISS51紧密捆绑的，由ISS51安装SMART MEDIA是三星公司提供的仿真模型，我们使用的也是三星公司的同类型存储卡。该模型可以用于验证软件操作SMART MEDIA的正确性和DMA Controller的接口时序。
DMA Controller是Mini Web卡硬件开发的一部分，将逻辑设计代码应用于仿真，既能检测逻辑设计的正确性，又能使整个仿真系统得以正常运转。
将上述硬件模型连接起来，产生下图所示硬件系统模型图：
图2. Mini Web卡硬件模块电路图
图2中U11为SMART MEDIA仿真模型，U4为DMA Controller模型。
虚拟网卡
做系统仿真，必须输入来自真实世界的激励，并将仿真系统的输出传递到真实世界。即便是不能连接到真实世界，也应该提供模拟真实世界的输入，并对仿真系统的输出进行检测和分析。
对于Mini Web卡来说，它和真实环境是通过网口连接的。使用虚拟网卡技术，能够将图3中的MAC C Model与虚拟网卡进行通讯。
对于运行在Windows系统上的应用程序来说，它并不知道网卡是虚拟的还是真实的，应用程序通过虚拟网卡收发数据，事实上是与仿真系统在进行网络通信。
这样就可以使用TFTP向Mini Web卡仿真系统传递网页文件，使用IE浏览Mini Web卡仿真系统中的网页，Mini Web卡的所有功能都能够被检验。
使用网络臭探器Sniffer可以监控虚拟网卡的报文流，方便协议调试。
仿真加速技术
软硬件联合仿真，影响仿真速度的瓶颈在HDL代码部分的仿真。如果不设法提高HDL代码部分的仿真速度，软件调试就非常低效。
提高硬件仿真速度的方法之一是软件硬件仿真采用事件同步，只在CPU访问IO时保持软件和硬件是同步的。
仿真加速方法之二是硬件仿真系统时钟休眠。对于Mini Web卡来说，只有DMA Controller是受时钟控制的，软件没有操作DMA Controller的期间，DMA Controller的运作是毫无意义的，所以可以在非DMA操作期间，对时钟进行休眠；ISS51在每次IO访问时，给出与上次IO访问的时间差，这个时间差经过处理可以作为时钟休眠的时间段。如果ISS51连续进行IO访问，就不会产生时钟休眠了。DMA Controller工作于查询方式，可以采用时钟休眠技术，而不会导致仿真与真实结果的不一致。方法之三是，缩短SMART MEDIA仿真模型中的一些长延时的时间参数。因为在等待SMART MEDIA进入就绪状态时，CPU必须连续查询IO，影响仿真速度。我们主要用于软件功能验证，这种修改也是可以接受的。
方法之四，在软件设计上，谨慎使用外部中断，因为一旦中断启动，ISS51需要在每个机器周期查询是否有中断信号，导致软件仿真和硬件仿真在每个指令上都进行同步，影响仿真速度。如果一定要使用外部中断，建议用C模型代替Verilog模型，这样可不影响仿真速度；或者由用户根据外部模块产生外部中断的时机，使用ISS51的控制命令，在恰当时刻使能ISS在一个普通PC （CPU为AMD速龙1000，SDRM512M 133），运行Mini Web卡仿真系统，使用PING命令测试Mini Web卡仿真系统的响应速度：
Reply from 10.10.112.76: bytes=32 time=64ms TTL=128
使用IE打开Mini Web卡仿真系统中的网页文件，感觉和拨号上网的速度差不太多。创建多个TFTP连接，同时向仿真系统传递或下载网页文件，同时使用IE进行网页浏览，都无响应中断现象出现。
总结
使用软硬件联合仿真，Mini Web卡不需要硬件就能进行全部功能的仿真，增强了系统设计成功的信心。软硬件联合仿真方便系统设计调整，可以在设计前期评估性能，方便软件和硬件的debug，是一个值得推广的技术。
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I. 求51系列单片机系统实验板的外文翻译,大概要3000字左右
8-Bit Microcontroller-AT89C51
Features
Compatible with MCS-51 Procts
4 Kbytes of In-System Reprogrammable Flash Memory
Enrance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Mode
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the instry standard MCS-51instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full plex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The idle Mode stops the CPU while allowing the RAM, timer/count- ers, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Configurations
Pin Description
VCC：Supply voltage.
GND：Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 may also be configured to be the multiplexed low- order address/data bus ring accesses to external program and data memory. In this mode P0 has internal pullups.
Port 0 also receives the code bytes ring Flash programming, and outputs the code bytes ring program verification. External pullups are required ring program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs.
Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes ring Flash programming and program verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pullups.
Port 2 emits the high-order address byte ring fetches from external program memory and ring accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal data memory that use 8-bit addresses (MOVX @ RI). Port 2 emits the cintents of the P2 special Function Register.
Port 2 also receives the high-order address bits and some control signals ring Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and programming verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address ring accesses to external memory. This pin is also the program pulse input (PROG) ring Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes.. Note ,however, that one ALE pulse is skipped ring each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro- gram memory. When the AT89C51is executing code from external pro- gram memory, PSEN is ac tivated twice each machine cycle, except that two PSEN activations are skipped ring each access to external data memory.
EA/VPP
External Access Enable. must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. EA should be strapped to VCC for internal program execu tions. This pin also receives the 12-volt programming enable voltage (VPP) ring Flash programming, for parts that re- quire 12-volt VPP.
XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2: Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the ty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on- chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Data Memory
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a l-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled ring S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register ring S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future procts to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers Control and status bits are contained in registers
T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers The indivial interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.